Senior AI STA Engineer, Sub-chip
Salary not listed • Israel, Yokneam • Full-time
Posted 1mo ago
About the job
NVIDIA is seeking experienced Physical Design Engineers to join our Networking Silicon engineering team. You will be instrumental in developing industry-leading high-speed communication devices, focusing on delivering the highest throughput and lowest latency. This role offers the opportunity to design groundbreaking chips in a professional and impactful environment within a technology-focused company.
Responsibilities
- Perform advanced AI Static Timing Analysis (STA) for complex chiplet and full chip levels.
- Utilize AI for timing optimization and data analysis within STA and Place & Route (PnR).
- Run and build STA tools for timing analysis and debugging.
- Use traditional STA tools like Prime Time, review and debug timing paths, understand constraints, and generate SDC and timing eco files.
- Identify convergence risks and collaborate with physical design, RTL, and DFT teams.
- Oversee full timing closure and quality approval from pre-layout STA modeling through signoff.
Requirements
- B.SC./M.SC. in Electrical Engineering.
- At least 5 years of hands-on STA experience.
- Experience with Prime Time and signoff methodologies.
- Ability to be a great teammate in a collaborative environment.
- AI tools orientation or a strong desire to learn AI.
- Experience with data collection and analysis.