IP Verification Engineer - GPU Core Pipeline
Salary not listed • India, Bengaluru • Full-time
Posted 8d ago
Remote Work Policy
On-site
Employment Type
Full-time
Categories
Machine Learning Engineer
About the job
NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We are united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”
Responsibilities
- Contribute to verifying graphics and compute features within an IP.
- Perform IP-level verification of GPU ASICs, including design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies.
- Develop test plans, tests, and verification infrastructure using UVM methodology, ensuring functional and code coverage of all RTL.
- Collaborate with HW architects and designers to ensure optimal implementation choices.
- Work with architects, designers, and other verification team members to accomplish tasks.
Requirements
- B.Tech./M.Tech. with 2+ years of relevant experience.
- Familiarity with Verilog, C++, and OOPs concepts.
- Experience in verification and test planning at the Unit level.
- Experience in developing and working in functional coverage-based constrained random verification environments.
- Good understanding of computer architecture concepts.
- Strong technical fundamentals with superior analytical and problem-solving skills.
- Knowledge in SystemVerilog or similar HVL.
- Experience in verification methodologies like UVM/VMM is highly desirable.
- Exposure to industry-standard verification tools for simulation and debug.
Benefits
- Competitive salaries
- Generous benefits package