Power Architect – AI SOC
Salary not listed • India • Full-time
Posted 10d ago
Remote Work Policy
On-site
Employment Type
Full-time
Categories
Machine Learning Engineer
About the job
EnCharge AI is developing a next-generation AI platform featuring a novel in-memory-computing architecture designed to significantly improve energy efficiency and performance for AI inference workloads. We believe that as AI demands evolve, the underlying infrastructure must also advance. Our team, comprised of experienced AI researchers, silicon and systems engineers, and architects, is backed by leading investors and is positioned to be a key player in the future of AI innovation.
Responsibilities
- Drive end-to-end PPA (Power, Performance, Area) excellence for next-generation AI semiconductor chips.
- Influence SoC architecture, RTL design, and physical layout to achieve industry-leading power efficiency for AI workloads.
- Develop and implement comprehensive SoC-level power and thermal management architecture.
- Influence microarchitecture, memory hierarchies, and dataflows to minimize dynamic and leakage power for AI inference and training.
- Review and guide RTL implementation to ensure alignment with power and timing goals.
- Collaborate with Physical Design teams on area constraints, floorplanning, and multi-voltage domain structures.
- Develop and fine-tune Physical Design recipes for synthesis, placement, clock tree synthesis, and routing to meet PPA targets.
- Partner with EDA vendors and internal teams to adopt and customize advanced power analysis tools.
- Develop custom scripts and design workflows to optimize power savings.
- Lead PPA analysis and trade-off discussions across RTL, architecture, and PD teams.
- Resolve complex bottlenecks to ensure silicon meets strict power budgets.
Requirements
- BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field.
- 12+ years of semiconductor experience with a deep focus on SoC architecture, low-power RTL design, and Physical Design (PD) implementation.
- Proven track record of delivering complex, high-performance silicon (AI accelerators, GPUs, or advanced SoCs) under stringent PPA constraints.
- Hands-on expertise with power intent (UPF/CPF) and industry-standard power estimation/analysis tools.
- Strong scripting and automation skills (Python, Tcl, Perl) for customizing EDA tool flows and PPA data analysis.
- Ability to look beyond block-level metrics to understand how architectural choices impact physical layout and thermal limits.
- Excellence in breaking down silos and collaborating with hardware, physical design, and software/firmware teams.
- Proactive in building custom methodologies to push chip efficiency boundaries.