Principal Design Verification Engineer
$180k - $255k • San Jose, California, United States
Posted 4d ago
About the job
SambaNova is seeking a Principal Design Verification Engineer to take ownership of the verification for their next-generation RDU, the core silicon powering their machine learning and AI systems. This senior individual contributor role involves defining the test plan, testbench architecture, coverage model, and sign-off criteria. You will also play a key part in shaping the team's infrastructure, reuse strategies, and overall verification practices. You will collaborate closely with principal engineers from design, architecture, compiler, and runtime teams, leveraging their experience to verify the chip against production ML workloads.
Responsibilities
- Own end-to-end verification for a major RDU subsystem, including test plan, testbench architecture, coverage model, and sign-off criteria.
- Develop and drive the coverage model for your area to closure before tape-out.
- Create testbench components, agents, checkers, and stimulus at block, full-chip, system, and gate levels.
- Act as the technical authority for your subsystem's verification, reviewing testbench design decisions and leading debug for complex failures.
- Manage regression health and failure triage for your area, focusing on root cause analysis.
- Verify both functional and performance aspects of the RDU.
- Advance the team's DV methodology through reusable infrastructure, verification IP integration, and AI-assisted workflows.
- Contribute to emulation and FPGA prototyping, and support silicon bring-up and post-silicon debug.
- Set the technical standard through design and DV reviews, and mentor other engineers to enhance the team's verification practices.
Requirements
- BS or MS in EE, CS, or CE with 7+ years of industry experience in ASIC design verification, or equivalent.
- Deep expertise in SystemVerilog and SVA with a standard methodology (UVM, OVM, or VMM).
- Proficiency in scripting with Python and C/C++.
- Proven experience with full-cycle DV ownership from test plan to tape-out on at least one complex ASIC or major subsystem, including coverage model ownership to closure.
- Experience verifying digital logic in CPUs, GPUs, SoCs, or comparably complex ASICs.
- Demonstrated ability to debug difficult, intermittent, or low-reproducibility pre-silicon failures to root cause.
- Evidence of technical leadership without formal authority, including setting direction in reviews, arbitrating testbench decisions, and mentoring engineers.
- Working knowledge of modern computer architecture and machine learning accelerators or SoCs.