Design Verification Engineer - Internal IP
$150k - $350k • Austin • FullTime
Posted 6mo ago
About the job
Etched is building hardware for frontier intelligence, focusing on inference. We are seeking a Design Verification Engineer to join our Internal IP DV team. You will be responsible for ensuring the custom IPs powering our chips, including systolic arrays, DMA engines, and NoCs, are robust, high-performance, and silicon-ready. This role requires creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
Responsibilities
- Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs.
- Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance.
- Debug complex datapath and protocol issues in RTL and testbench environments.
- Collaborate with architects and designers to validate functionality and design intent.
- Partner with SW, FW, and emulation teams for end-to-end bring-up and debug coverage.
- Contribute to reusable DV infrastructure, coverage models, and methodology improvements.
Requirements
- Proficiency with UVM and SystemVerilog.
- Strong debugging and problem-solving skills for complex digital designs.
- Solid knowledge of computer architecture and digital design fundamentals.
- Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch + dinner in our office
- Unlimited compute budget subject to ROI justification