1 open role mentioning Verilog/SystemVerilog
OpenAI
We are seeking a Software Engineer to develop the research infrastructure and tooling that will enable OpenAI models to design silicon. This role involves transforming chip-design workflows into robust environments for reinforcement learning and evaluation, and simplifying the process for researchers to conduct experiments and iterate on new ideas. You will bridge software engineering, tool integration, and open research challenges, leveraging strong coding fundamentals, clear technical judgment, and independent execution. While prior chip-design experience is beneficial, domain knowledge can be acquired alongside our hardware specialists.
$266k - $468k
