Physical Design Engineer, Forward Deployed Engineering
Remote • San Francisco • FullTime
Posted 4d ago
Remote Work Policy
Fully remote
Employment Type
FullTime
Categories
Applied AI Engineer
About the job
OpenAI's Forward Deployed Engineering team is seeking a senior Physical Design Engineer to partner with leading semiconductor companies. This role focuses on deploying AI systems across the chip design lifecycle, from design to physical design. Initially, you will serve as the team's subject matter expert in physical design, advising on backend implementation, testing AI-assisted solutions, and improving customer-facing technical work. Over time, the role will expand to encompass broader Forward Deployed Engineering responsibilities, including direct customer partnerships, shaping deployment strategies, building AI systems, and driving technical workstreams.
Responsibilities
- Serve as the physical design subject matter expert for semiconductor customer engagements.
- Partner with FDEs during customer discovery and scoping to define solution hypotheses and technical plans.
- Support customer-facing technical conversations as a trusted advisor.
- Shape AI-assisted solutions for physical design workflows, including floorplanning, place and route, and timing closure.
- Guide feasibility and integration decisions across the chip design lifecycle.
- Partner with FDEs and customer SMEs to curate evaluation datasets and acceptance criteria for physical design use cases.
- Build or guide prototypes, benchmarks, and internal tools to validate opportunities.
- Educate and mentor the FDE team on physical design concepts and EDA tooling.
- Surface customer signal to Product and Research to influence roadmap and platform capabilities.
- Progressively take on broader FDE responsibilities, including customer discovery, solution architecture, and production deployment.
Requirements
- BS with 7+ years, MS with 5+ years, or equivalent industry experience in physical design, physical implementation, or backend signoff for complex ASIC or SoC programs.
- Demonstrated success bringing complex designs through tapeout, with hands-on experience in floorplanning, place and route, CTS, timing closure, power analysis, physical verification, and signoff.
- Deep familiarity with industry-standard EDA tools and flows for synthesis, PNR, STA, physical verification, equivalence checking, and power analysis.
- Strong understanding of how physical design intersects with microarchitecture, RTL, verification, design methodology, libraries/PDKs, and system-level PPA trade-offs.
- Strong communication and collaboration skills, with the ability to translate deep technical trade-offs clearly.
- Comfortable operating as a consultative expert and advisor.
- Strong scripting and automation skills in Python, Tcl, or similar.
- Excited to grow beyond domain SME responsibilities into a broader Forward Deployed Engineering role.