Senior System Integration Engineer, Memory
$196k - $311k • US, CA, Santa Clara
Posted 26d ago
About the job
NVIDIA's Silicon Co-Design Group (SCG) is seeking a Senior Memory Systems Engineer to lead the integration of HBM and LPDDR in sophisticated SoCs. This role spans the entire product development lifecycle, from architecture definition to silicon bringup and release, focusing on resolving complex system-level memory challenges. The engineer will be instrumental in ensuring memory subsystems meet performance, power, and reliability targets for next-generation products.
Responsibilities
- Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs.
- Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware.
- Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency.
- Debug and resolve memory training, calibration, SI/PI, and system-level stability issues.
- Define validation, characterization, and issue-tracking plans across chip programs.
Requirements
- BS or MS in EE/CE or equivalent experience.
- 12+ years in HBM, LPDDR, or high-speed memory systems with hands-on depth in silicon bringup, characterization, and debug at scale.
- Deep command of SI/PI, timing, margining, and memory training behavior.
- Multi-functional fluency to work across design, package, firmware, validation, and product teams.
- System-level instinct to identify and resolve potential product problems related to memory behavior.
Benefits
- Equity
- Benefits