Senior Performance Modeling Architect, CPU Fabric and LLC
$152k - $288k • Remote • US, CA, Santa Clara
Posted 1d ago
Job Location
US, CA, Santa Clara
Tech Stack
Remote Work Policy
Fully remote
Categories
Machine Learning Engineer
About the job
We are seeking a Senior Performance Modeling Architect to define and enhance our next-generation CPU Cache Hierarchies and interconnects. This role offers a unique opportunity to develop scalable solutions that bridge the high-reliability, low-latency requirements of Automotive systems with the efficiency and density demands of Data Center environments. You will be instrumental in creating the core models that manage data flow across our silicon, ensuring our L3/System Caches and coherent fabrics meet ambitious performance targets.
Responsibilities
- Develop and maintain high-fidelity, cycle-accurate performance models (C++/SystemC) for coherent interconnects and large-scale shared caches.
- Model and analyze performance bottlenecks across various scales, from automotive SoCs to multi-mesh data center architectures.
- Evaluate the performance impact of different coherency protocols and snooping filters.
- Run and analyze industry-standard benchmarks to inform architectural trade-offs.
- Collaborate with build and verification teams for model-silicon correlation and with software teams for hardware topology optimization.
Requirements
- Master's or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience) with a focus on architecture and 5+ years of experience.
- Strong understanding of CPU microarchitecture, memory consistency models, and cache coherency protocols.
- Proven experience in C++ or SystemC for cycle-accurate or functional modeling.
- Proficiency in Python or similar scripting languages for data processing, visualization, and simulation automation.
- Understanding of Network-on-Chip (NoC) topologies, credit-based flow control, and arbitration logic.
Benefits
- Equity
- Benefits