Principal EDA R&D Engineer
$232k - $368k • Remote • US, CA, Santa Clara
Posted 1mo ago
Job Location
US, CA, Santa Clara
Tech Stack
Remote Work Policy
Fully remote
Categories
AI Agent Engineer
About the job
NVIDIA is seeking a Principal EDA R&D Engineer to lead the research, architecture, and development of next-generation hardware formal verification tools. This role involves pioneering advancements in core formal verification engines, enhanced by Agentic AI frameworks. You will craft collaborative, autonomous AI agent networks to extend formal tools, enabling them to automatically break down large builds, coordinate solver strategies, synthesize complex properties, and debug execution traces at an unprecedented scale. The position demands deep algorithmic knowledge, rigorous industrial software engineering, and a proven track record of delivering production-grade EDA tools.
Responsibilities
- Architect, construct, and advance new formal verification algorithms.
- Design, develop, and deploy multi-agent AI systems for autonomous analysis and optimization of designs.
- Develop intelligent orchestration layers for autonomous AI agents to handle complex design challenges.
- Develop intelligent engines for automatic generation of System Verilog Assertions from natural language specifications.
- Drive features from algorithmic research through implementation in high-performance C/C++ environments.
- Ensure seamless integration of new features into commercial EDA tool suites.
Requirements
- Ph.D. or Master’s degree or equivalent experience in a quantitative field.
- Minimum of 15 years of professional R&D experience building commercial or advanced academic EDA hardware verification tools.
- Deep mathematical and hands-on understanding of formal methods (e.g., BMC, PDR/IC3, abstract interpretation, theorem proving).
- Expert-level proficiency in Modern C/C++ (C++17/20) with a focus on performance, memory optimization, and multi-threading.
- Proven experience building or researching Agentic AI pipelines, multi-agent frameworks, tool-use execution, and prompt engineering for structured code or hardware descriptions.
- Experience with RTL languages (System Verilog, VHDL, Verilog) and System Verilog Assertions (SVA).
Benefits
- Equity
- Benefits