Power Validation Engineer
San Jose • FullTime
Posted 5mo ago
About the job
Etched is building hardware for frontier intelligence, focusing on co-designing chips, racks, software, and manufacturing to deliver best-in-class throughput and latency for inference workloads. Backed by significant investment and staffed by leading engineers, Etched is redefining the infrastructure layer for the AI industry. We are seeking a Power Validation Engineer to take ownership of the end-to-end power characterization of our ASIC and mezzanine card platform, from initial silicon bring-up through production qualification. This role involves designing measurement methodologies, building test benches, and directly influencing silicon, package, and system design decisions based on findings.
Responsibilities
- Design and execute power measurement campaigns across all voltage rails under realistic LLM inference and power virus workloads, characterizing power envelopes and defining derating curves.
- Validate power delivery network (PDN) performance, including VRM load step response and impedance, translating measurements into actionable feedback for PCB and package design teams.
- Profile power transient events and correlate them with on-die performance monitor data, building automated power sweep frameworks.
- Run extended stress workloads to identify reliability risks and throttling behavior, instrumenting thermal profiles and supporting overseas partners.
- Validate power sequencing, PMBus telemetry accuracy, and BMC alert thresholds across various scenarios, owning power-related pass/fail criteria.
- Feed characterization data back to RTL and physical design teams for DVFS policy, clock gating coverage, and leakage optimization, writing precise validation reports.
- Lead the electrical characterization, validation, and qualification of the on-board system-level power distribution network.
- Provide critical support to design engineers through debug, component validation, and failure analysis for released products.
- Develop and implement automated/scripted test procedures for general qualification and testing of Devices Under Test (DUTs).
- Collect, analyze, and aggregate test data to support data-driven engineering decisions and generate reports.
- Collaborate with hardware designers and diagnostics development teams to understand new project architectures and ensure testing and debug support.
Requirements
- Bachelor’s degree in Electrical Engineering or a related field.
- Deep understanding of ASIC and system-level power delivery, including VRM topology, PDN impedance, decoupling strategy, and transient response.
- Hands-on bench experience using precision shunts, isolated differential probes, and VNA-based PDN impedance measurement.
- Expertise with multi-phase solutions with high dynamic content and low tolerance.
- Experience with VR tuning to a defined power test plan.
- Ability to design experiments that isolate root cause in complex hardware-software stacks.
- Strong oscilloscope and lab instrument fluency, including triggering on rare transient events and correlating multi-channel captures.
- Track record of finding bugs that surface under specific workload or environmental conditions.
- Relevant experience with Silicon bring ups.
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2,500 per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification